There is a lot of literature already available describing well-structured approach for embedded design and implementation of Application Specific Integrated Processor (ASIP) micro processor core.
This concept features hardware structured approach for implementation of processor core from minimal instruction set, encoding standards, hardware mapping, and micro architecture design,coding conventions, RTL,verification and burning into a FPGA.
The goal is to design an ASIP processor core (Micro architecture design and RTL) which can perform DSP task, e.g., FIR. There port is a well structured approach of design and implementation of an ASIP DSP processor for DSP applications like FIR. This report contains design flow starting from Instruction set design,micro architecture design and RTL implementation of the core. Details of the power simulations of FPGA are also listed and analyzed.
This concept features hardware structured approach for implementation of processor core from minimal instruction set, encoding standards, hardware mapping, and micro architecture design,coding conventions, RTL,verification and burning into a FPGA.
The goal is to design an ASIP processor core (Micro architecture design and RTL) which can perform DSP task, e.g., FIR. There port is a well structured approach of design and implementation of an ASIP DSP processor for DSP applications like FIR. This report contains design flow starting from Instruction set design,micro architecture design and RTL implementation of the core. Details of the power simulations of FPGA are also listed and analyzed.
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